This invention relates to the field of semiconductor memories. More particularly, this invention relates to providing a smaller dual port SRAM memory cell.
A typical random access memory (RAM) architecture consists of an array of memory cells. Each cell can store one bit of information. The array is arranged as rows and columns of memory cells. Each row is also referred to as a wordline. Each column is also referred to as a bitline. A memory device containing such an array with 2m rows and 2n columns can store 2mxe2x80xa2n bits of information. If fabrication of such an array requires one unit of area, then the memory cell density for such an array is 2mxe2x80xa2n cells per unit area.
In systems which require memory devices, storage capacity and operational speed of the memory are important attributes. From a system throughput standpoint, the accessibility of the memory device is another important attribute. Storage capacity refers to the amount of data that a memory device can store. Operational speed refers to the speed at which the memory device can store or retrieve data. Accessibility is largely dependent upon the architecture of the system. Generally, the system throughput increases when more than one system device can directly access the memory device. The system throughput is generally further increased when more than one device can simultaneously access the memory.
Since a memory device typically contains one or more arrays of memory cells, the storage capability of a memory device is largely dependent upon the size of a memory cell. The size of a cell given a fixed number of components will change as fabrication technology evolves. However, any reduction in the size of a memory cell will permit fabrication of memory devices containing an increased density of memory cells. A reduction in cell area will permit an increase in an array""s cell density by a factor approaching the reduction factor.
Thus, for example, a cell which uses 40% of the area of another cell will have a reduction factor of 2.5. Therefore, an array of the smaller cells may have a cell density approaching 2.5 times that of an array of the larger cells.
Storage capacity is directly related to cell density. Given a fixed unit of area for an array of memory cells, a reduction factor of 2.5 will permit memory devices constructed with the smaller cells to have up to 2.5 times the storage capacity of memory devices constructed with the larger cells.
System access speed can often be dramatically increased through the use of a dual port memory architecture. A dual port memory has two access ports so that more than one system device may directly access the memory. A single port memory permits direct coupling to only one system device such that other system devices must contend for the port in order to gain access to the memory. By permitting direct coupling to more than one system device, overall system performance is usually enhanced since a dual port architecture decreases the contention for access to a port of the memory.
Examples of memory devices utilizing a dual port memory architecture include dual port static random access memories (SRAMs) and first-in-first-out (xe2x80x9cFIFOxe2x80x9d) buffers. An integrated circuit dual port memory device may include an array of dual port memory cells. One such prior art dual port cell is illustrated in FIG. 1.
Traditional dual port memory cells suffer from a number of disadvantages. One disadvantage of the prior art dual port memory cell is that the layout size of such a cell is approximately 2-2.5 times the size of a single port cell constructed using the same fabrication technology. Another disadvantage of the prior art dual port memory cell is that a pair of bitlines are required for each port due to the differential nature of the cell.
Another method of achieving the effect of a dual port memory device in practice is to use an array of single port memory cells inside the dual port memory device. Such a prior art single port memory cell is illustrated in FIG. 2. In this example, the ports of the memory device are multiplexed before gaining access to the memory array. Thus two devices are contending for access at the device level as opposed to at the level of a memory cell in the array.
One disadvantage of using multiplexed single port memory cells is that the multiplexing circuitry uses space which could otherwise be utilized to construct more memory cells. In addition, the multiplexing function for accessing a single port cell is slower than the direct access method using a dual port memory cell. This typically results in a slower operational speed for the memory device. The slower operational speed of the memory tends to negatively affect the throughput of the entire system if memory accesses are frequently requested.
A single ended dual port memory cell is described. The memory cell can store a bit of data received from one of a first port and a second port. The first and second ports can simultaneously detect the stored bit.
The single ended dual port memory cell can be used in applications where one port is dedicated for read operations and another port is dedicated for write operations. In such applications, the single ended dual port memory cell functions as a single ended simplex dual port memory cell and the ports may be optimized for their respective dedicated read or write operations.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.